1. Field of the Invention
This invention relates to a display device, which makes a selection between two display modes; a moving image mode where an image signal consecutively inputted is consecutively displayed and a still image mode where an image signal stored in a frame memory is displayed.
2. Description of the Related Art
With the spread of personal digital assistant (PDA) in recent years including cellular phone and laptop personal computer, the liquid crystal display (LCD) device and electric luminescence (EL) display device have been used widely as they have relatively small power consumption.
FIG. 4 shows a circuit diagram of an active matrix LCD as an example of a conventional display device. In the active matrix display device, a controlling circuit 200 is connected to a LCD panel 100.
The LCD panel 100 comprises a first substrate with a plurality of pixel electrodes and a second substrate with a single common electrode 10 facing to a plurality of the pixel electrodes with a liquid crystal sandwiched between the first and second substrates. On the first substrate, a plurality of the pixel electrodes 1 and a pixel TFT 2 for switching having a thin film transistor (TFT) for each of the pixel electrodes are placed in a matrix configuration. A gate line 3 is placed in the row direction and a data line 4 is placed in the column direction of the matrix of the pixel electrodes 1. The gate line 3 is connected to the gate of the each pixel TFT 2 and the data line 4 is connected to the drain of the each pixel TFT 2. Also, the gate line 3 is connected to a gate line shift register 5 placed near the display area. The data line 4 is connected to a data bus line 7 through a data line selection TFT 6, the gate of which is connected to the output terminal of a data line shift register 8. The data line selection TFT 6 and the data line shift register 8 configure a data line driver for consecutively selecting the data line 4 and supplying the data signal. Also, a storage capacitor 9 for storing a pixel voltage is placed for each of the pixel along with a liquid crystal capacitor placed in parallel.
The control circuit 200 has a data processing unit 21, a CPU interface 22, a timing controller 23, and a digital-analog converter (DAC) 24. When an analog image signal is inputted, the data processing unit 21 produces a signal suitable for the LCD panel by performing the sampling with an adequate timing, converting the signal into digital signal, adjusting the brightness and contrast, and applying the gamma correction. The CPU interface 22 receives a command of a CPU, not shown in the figure, which controls a device with a LCD such as PDA and cellular phone, and sends the controlling signal out to each part of the device based on the command received. The timing controller 23 outputs various kinds of timing signal to the LCD panel 100 based on a vertical start signal and a horizontal synchronous signal extracted from the image signal. The DAC 24 converts a RGB digital data outputted from the data processing unit 21 into the voltage suitable for the pixel voltage of the LCD panel 100 and outputs the converted voltage.
Next, the operation of the active matrix LCD, along with the driver control signal, will be explained. FIGS. 5 and 6 are the timing charts showing several timing signals. A vertical synchronous signal Vsync is a clock outputting a “high level”0 every time when a vertical synchronous period begins for indicating the start of one frame period. A vertical start signal STV is inputted to the gate line shift register 5. The gate line shift register 5 is a shift register, which starts the operation in response to the vertical start signal STV. A gate line clock CKV is inputted to the gate shift register 5 and the shift register for each of the gate line clock CKVs consecutively supplies the gate signal to the gate line 3. Half a cycle of the gate line clock CKV is equal to the horizontal synchronous period. Entire pixel TFTs 2 connected to the gate line 3 provided with the gate signal turn on. The horizontal start signal STH is inputted to the data line shift register 8 of the date line driver. The data line shift register 8 starts the operation in response to the horizontal start signal STH. A data line clock CKH is inputted to the data shift register 8 and the out put of the data shift register 8 changes for each of the data line clock CKHs, consecutively supplying the data line selection signal to the data line selection TFT 6. The data line selection TFT 6 provided with the data line selection signal turns on and the data signal DATA is supplied to the pixel electrode 1 from the data bus line through the data line 4 and the pixel TFT 2. As shown in the figure, there is a plurality of the data bus lines 7. By supplying the same gate signal to the data line selection TFT 6 corresponding to each of the data bus lines, the pixel voltage is simultaneously applied to a plurality of the pixel electrodes 1. After completing the selection of all the data lines 4 by the data shift register 8, the gate line clock CKV is inputted again for selecting the next gate line 3. After completing the selection of all the gate lines 3 by the gate shift register 5, display, of one screen image is completed. Every time data for one row, or, for example, the data for 176 pixels is written, there is a horizontal blanking period, where no data is inputted for a certain period of time. Also, every time the data for entire pixels, or the data for 220 rows, is written, there is a vertical blanking period, where no data is inputted for a certain period of time (for several horizontal period). During the vertical blanking period, the next vertical synchronous signal Vsync is inputted, starting the next frame and repeating the same procedure mentioned above from the beginning.
In the PDA such as cellular phone, the reduction of the power consumption is indispensable for a longer operation period. Therefore, in cellular phone, a display device with a frame memory capable of storing image data for one screen display is widely used and the display is made by using the data stored in the frame memory. FIG. 7 shows the circuit diagram of the display device with a frame memory. The same components as those in FIG. 4 have the same reference numerals as in FIG. 4 and the explanation about these configurations will be omitted. The frame memory 25 is a SRAM, which stores the digital image data of the entire pixels of the liquid crystal panel 100 inputted through the CPU interface 22. The image data stored in the frame memory 25 is converted into the pixel voltage by the DAC 24 and then supplied to each of the pixel electrodes.
When the image data stored in the frame memory 25 is displayed, it is necessary to produce the timing signal because the timing signal such as the vertical synchronous signal Vsync is not supplied from outside. An oscillator 26 produces a base clock and supplies it to the timing controller 23. The timing controller 23 produces the data line clock CKH by multiplying the frequency of the basic clock. A counter in the timing controller counts the base clock for outputting one pulse for a predetermined number of data line clocks, producing the horizontal start signal STH and the gate line clock CKV. Also, another counter counts the base clock, producing the vertical start signal STV.
One of the advantages of the display device with the frame memory 25 is that the power consumption is relatively small since there is no need to input the display data from outside. However, it is necessary to, first, store the image data in the frame memory 25, requiring a certain amount of time for storing. Thus, the device does not have an enough imaging speed for displaying a moving image.